In this paper the relationship between memory contention and the number of module in a parallel or interleaved memory generally used in a multiprocessor system is analysed and mathematical models of efficient memory bandwidth for 2n module and prime module are set up respectively. 本文对多处理机中通常使用的并行或交叉存储器,进行了模的个数对存储冲突的影响的分析,并建立了在模块数分别为2~n和素数时存储有效宽度的数学模型。